1. Field of the Invention
The present invention relates to the formation of trenches in the surface of a semiconductor wafer which are filled with dielectric material for isolating regions of the semiconductor.
2. DESCRIPTION OF THE PRIOR ART
Known techniques for isolation trench filling in semiconductor technology includes the step of blanketing the entire chip area with the filling material and, hence, requires back-etching for removal of excess material outside of the trenches. Back-etching is time-consuming, expensive, and difficult to control.
Examples of prior art techniques are found in the following references.
U.S. Pat. No. 4,385,975, issued May 31, 1983 to Chu et al entitled METHOD OF FORMING WIDE, DEEP DIELECTRIC FILLED ISOLATION TRENCHES IN THE SURFACE OF A SILICON SEMICONDUCTOR SUBSTRATE describes a method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.
U.S. Pat. No. 4,307,180 issued Dec. 22, 1981 to Pogge entitled PROCESS OF FORMING RECESSED DIELECTRIC REGIONS IN A MONOCRYSTALLINE SILICON SUBSTRATE describes a method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO.sub.2 layer, openings formed through the polycrystalline layer and SiO.sub.2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO.sub.2 layer.
U.S.Pat. No. 4,016,017 issued Apr. 5, 1977 to Aboaf et al entitled INTEGRATED CIRCUIT ISOLATION STRUCTURE AND METHOD FOR PRODUCING THE ISOLATION STRUCTURE describes a process for fabricating a semiconductor device having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer.
U.S. Pat. No. 4,104,086 issued Aug. 1, 1978 to Bondur et al entitled METHOD FOR FORMING ISOLATED REGIONS OF SILICON UTILIZING REACTIVE ION ETCHING describes a method for isolating regions of silicon involving the formation of openings that have a suitable taper in a block of silicon, thermally oxidizing the surfaces of the openings, and filling the openings with a dielectric material to isolate regions of silicon within the silicon block. The method is particularly useful wherein the openings are made through a region of silicon having a layer of a high doping conductivity.
U.S. Pat. No. 4,404,736 issued Sept. 20, 1983 to Koshino et al entitled METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE OF MESA TYPE describes a method for manufacturing a semiconductor device of mesa type which comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.
U.S. Pat. No. 4,404,735 issued Sept. 20, 1983 to Sakurai entitled METHOD FOR MANUFACTURING A FIELD ISOLATION STRUCTURE FOR A SEMICONDUCTOR DEVICE describes a method for forming a field isolation structure for semiconductor device, in which a groove is formed in a semiconductor substrate, an insulating layer is formed on the substrate at least in the groove, a glass layer or a silicon layer is formed thereon, and thereafter a high energy beam such as a laser beam is irradiated onto the glass or silicon layer to selectively heat the same thereby to melt or fluidify the layer and let the same flow into the groove is disclosed. A smooth and flat surface is obtained through the above melting process, which also prevents electrical breaks in wiring layers formed thereon. The method is particularly suited to producing small field isolation structures thus improving the integration density of the device.
U.S. Pat. No. 4,420,874 issued Dec. 20, 1983 to Funatsu entitled METHOD OF PRODUCING AN IIL SEMICONDUCTOR DEVICE UTILIZING SELF-ALIGNED THICKENED OXIDE PATTERNS describes a semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.
The prior art listed above is representative of the state of the art prior to the present invention and does not anticipate or make obvious the inventive features described hereinbelow.